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C00002 00002	A chip for the 3n+1 function
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A chip for the 3n+1 function

	Designing such a chip looks like a good exercise for the
nmos design technique discussed in Mead and Conway.

Here are some considerations:

#. the chip is controlled by a computer or microcomputer.  Maybe it
should be controlled by the KL.

#. Is 40 bits the right word length?

#. It can compute action sequence (see threen.lsp[e80,jmc]) and
residue.  Therefore it needs 2 extra registers.
There is a shift register which propagates whether to shift right
or multiply by 3/2.  As this register moves out the right it becomes
the action sequence.  If it were to be an output, it would probably
have to be taken off in parallel.

#. The logic should be synchronous since all steps take the same
amount of time.

#. detects overflow

#. uses unpropagated carries, so can do an add per cycle.

#. can do predetermined number of cycles.

#. maybe saves state occasionally, so can be asked to back up.  What
else did I have in mind when I thought of this?

Numbers with unpropagated carries should be good for FFT chips,
since the extra hardware shouldn't be harmful and the process
wants to be fast.